TY - GEN
T1 - A design platform for reconfigurable architecture and its application to watermarking system
AU - Dalbouchi, Roukaya
AU - Elhaji, Majdi
AU - Zitouni, Abdelkrim
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/7
Y1 - 2018/12/7
N2 - This paper presents a novel platform for reconfigurable architecture design. This platform contains a design that allows modeling and implementation of hardware architecture. We have nominated a generic design flow for partial and dynamic reconfigurable architecture (GDF4PDR). This flow is able to support any type of application. in addition, it is compatible with the Xilinx design flow and does not require the addition of other hardware or software elements. It is based on three elements, the reconfigurable model, the application and the mapping strategy between these elements. The comparison results show that the proposed flow is more generic and characterized by a high abstraction level modelling. The aim is to offer a platform that provides a good instance of architecture that meets compromises reconfigurations/performance. To validate the proposed platform a video watermarking application has been used. Experimental results show that the proposed design flow provides an architecture with a small reconfiguration time while ensuring optimal hardware implementation in terms of resources.
AB - This paper presents a novel platform for reconfigurable architecture design. This platform contains a design that allows modeling and implementation of hardware architecture. We have nominated a generic design flow for partial and dynamic reconfigurable architecture (GDF4PDR). This flow is able to support any type of application. in addition, it is compatible with the Xilinx design flow and does not require the addition of other hardware or software elements. It is based on three elements, the reconfigurable model, the application and the mapping strategy between these elements. The comparison results show that the proposed flow is more generic and characterized by a high abstraction level modelling. The aim is to offer a platform that provides a good instance of architecture that meets compromises reconfigurations/performance. To validate the proposed platform a video watermarking application has been used. Experimental results show that the proposed design flow provides an architecture with a small reconfiguration time while ensuring optimal hardware implementation in terms of resources.
KW - Dynamic reconfiguration
KW - FPGA
KW - Partial reconfiguration
KW - Reconfigurable architecture
KW - video watermarking
UR - https://www.scopus.com/pages/publications/85060610715
U2 - 10.1109/SSD.2018.8570442
DO - 10.1109/SSD.2018.8570442
M3 - Conference contribution
AN - SCOPUS:85060610715
T3 - 2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
SP - 195
EP - 201
BT - 2018 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th International Multi-Conference on Systems, Signals and Devices, SSD 2018
Y2 - 19 March 2018 through 22 March 2018
ER -