A low power network interface for network on chip

In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ many techniques able to hibernate switchings while no communication is avilable. In this papper, we try to reduce the power dissipation of NoC by reducing the network interface power. We present a hardware design of a low power Network interface design. The low power is obtained by the implementation of a mechanism based on stoppable clock technique for power saving. The stoppable clock technique allows us to shut down each sub module when it is not under running. Experimental results show that adaptability and stoppable clock technique aspects integrated in the proposed NI allow a significant reduction in terms of power while increasing the area.