TY - GEN
T1 - A parallel processing architecture for FSS block-matching motion estimation
AU - Dhahri, Salah
AU - Zitouni, Abdelkrim
AU - Tourki, Rached
PY - 2011
Y1 - 2011
N2 - Motion Estimation (ME) is a key factor for achieving enhanced compression ratio. However, ME involves high computational complexity. The main goal is to reduce the execution time without reducing image quality. In this paper, a proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method develops an architecture which using 9 processing-elements (PE) and processes them in parallel. The architecture has been simulated and synthesized with VHDL and ASIC (CMOS 45nm). Synthesize results show that the proposed architecture achieves a high performance for real time motion estimation.
AB - Motion Estimation (ME) is a key factor for achieving enhanced compression ratio. However, ME involves high computational complexity. The main goal is to reduce the execution time without reducing image quality. In this paper, a proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method develops an architecture which using 9 processing-elements (PE) and processes them in parallel. The architecture has been simulated and synthesized with VHDL and ASIC (CMOS 45nm). Synthesize results show that the proposed architecture achieves a high performance for real time motion estimation.
UR - https://www.scopus.com/pages/publications/80054830295
U2 - 10.1109/CCCA.2011.6031442
DO - 10.1109/CCCA.2011.6031442
M3 - Conference contribution
AN - SCOPUS:80054830295
SN - 9781424497959
T3 - 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
BT - 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
T2 - 2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
Y2 - 3 March 2011 through 5 March 2011
ER -