@inproceedings{9dbc02e65d604fc0bbd377d1e3a72c43,
title = "Design and performance evaluation of on chip network with transaction level modeling",
abstract = "Networks-On-Chip (NoC) are appropriate solutions to connect the increasing number of components being integrated into Systems-on-Chip. To simulate such systems at early design stage, abstraction techniques like Transaction Level Modeling (TLM) are used to describe the communication. In this paper, three different mesh 2D sizes are evaluated using SystemC TLM2 with a single transaction and reduced accuracy. Register Transfer Level (RTL) model and Loosely Timed (LT) Transaction Level models are compared.",
keywords = "Network on Chip, TLM router, Traffic pattern, Transaction Level Modeling",
author = "Nourddine Abid and Wissem Chouchene and Brahim Attia and Abdelrim Zitouni and Rached Tourki",
year = "2011",
doi = "10.1109/ICM.2011.6177373",
language = "English",
isbn = "9781457722073",
series = "Proceedings of the International Conference on Microelectronics, ICM",
booktitle = "2011 International Conference on Microelectronics, ICM 2011",
note = "2011 23rd International Conference on Microelectronics, ICM 2011 ; Conference date: 19-12-2011 Through 22-12-2011",
}