Implementation of a fast and low power 3SS algorithm for H.264 video coding

The motion estimation is considered one of the most effective techniques to significantly reduce the throughput required by a video codec. This step is the most expensive in computation time for the H264 standard. In this paper, we present an efficient VLSI architecture design using Three Steep Search (TSS) algorithms. In this design, we employ nine parallel processing element with are controlled by a state machine. However, the implementation of State machine makes the design very simple and cost effective. Our architecture has been simulated and synthesized using a VHDL language and ISE 9.1 tools respectively. Experiments show that the design can operate at frequencies up to 75 MHz and low power consumption.