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Network interface sharing for SoCs based NoC

  • Brahim Attia*
  • , Wissem Chouchene
  • , Abdelkrim Zitouni
  • , Rached Tourki
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The demand for IP reuse and system level scalability in System-on-Chip designs is growing. Network-on-chip constitutes a viable solution space to emerging SoC design challenges. In this paper, we present a configurable Network Interface(NI) architecture design approach with smaller area and lower power. The small area is achieved by memory resources sharing in the three modes used by the OCP IP or by many IPs connected to the NI. The low power is obtained by the implementation of a mechanism based on two level of gated clock for power saving. Experimental results show that adaptability, FIFO sharing, and gated clock aspects integrated in the proposed NI allow a significant reduction in terms of area and power.

Original languageEnglish
Title of host publication2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
DOIs
StatePublished - 2011
Externally publishedYes
Event2011 International Conference on Communications, Computing and Control Applications, CCCA 2011 - Hammamet, Tunisia
Duration: 3 Mar 20115 Mar 2011

Publication series

Name2011 International Conference on Communications, Computing and Control Applications, CCCA 2011

Conference

Conference2011 International Conference on Communications, Computing and Control Applications, CCCA 2011
Country/TerritoryTunisia
CityHammamet
Period3/03/115/03/11

Keywords

  • Network Interface
  • Network-on-Chip
  • OCP
  • sharing

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